Low power memory module using restricted RAM activation

ABSTRACT

A memory module for an electronic device is disclosed which provides means for reducing the amount of power necessary to access a desired number of data bits. This provides a design of memory modules which requires fewer DRAMs to be turned on during a read or write cycle than present module designs, thereby using much less power.

FIELD OF THE INVENTION

[0001] This invention relates to packaging configurations for integratedcircuit devices (ICs). The packaging configuration is directed to logicarrays such as memory modules for computers or other electronic devices.More specifically, it describes an improvement to the design of memorymodules which requires fewer DRAMs to be turned on during a read orwrite cycle than present module designs, thereby using less current.

BACKGROUND OF THE INVENTION

[0002] Current generation single in-line memory modules (SIMMs) forcertain brands of computers use eight one-megabit (1M) dynamic randomaccess memories (DRAMs) arranged in a x1 configuration (having one dataout signal), which supplies the computer with one megabyte (MB) ofmemory. Since the DRAMs are arranged in a x1 configuration, one data bitcan be extracted from each chip at a time. When a module with eight 1Mx1DRAMs is installed in a computer capable of handling eight bits of dataat a time (i.e. an 8-bit computer), it accesses all eight DRAMs on amodule simultaneously, thereby receiving the eight bits of data it iscapable of handling. In 16-bit computers, -modules containing eight 1Mx1DRAMs are installed in groups of two in the computer. To obtain the 16bits of data the computer is capable of handling, all 16 DRAMs areaccessed simultaneously, and the computer receives one bit of data fromeach DRAM for a total of 16 data bits. Each time a 1Mx1 DRAM isaccessed, it requires about 80 mA of current to be supplied. To accessthe 16 DRAMs simultaneously requires approximately 640 mA of current permodule, or 1,280 mA total.

[0003] Some SIMMs use 1Mx4 DRAMs, with each DRAM having four bits ofdata. A module using two 1Mx4 chips supplies 1 MB of memory, as does amodule using eight 1Mx1 chips. A module with two 1Mx4 devices isfunctionally equivalent to a module using eight 1mx1 devices, but hasfewer parts, thereby being easier to assemble and somewhat more reliabledue to fewer solder joints. There is not much power savings using amodule with two 1Mx4 DRAMs over a module using eight 1Mx1 DRAMs, as allthe devices on either module are turned on each time one of the devicesis accessed in order to access eight data bits, and to access two 1Mx4DRAMs requires about as much power as accessing eight 1Mx1 DRAMs.

[0004] In most computers, addressed words are an even number of bits,such as eight, sixteen or thirty two bits. This fits neatly into memoryarray blocks which use x4 chips. This convenient arrangement iscomplicated by the fact that a system of memory parity has proven to bevery effective in error detection. The parity is an additional bit foreach word, so that an eight bit word (“byte”) is addressed as nine bits,the ninth bit being parity.

[0005] Reducing power consumption in a computer or other electronicdevice is a design goal, as overtaxing a computer's power supply is acommon concern. With the addition of modem cards, memory boards,graphics cards, hard disk controller cards, printer buffer cards, andmouse cards, the chances of burning out the computer's power supply fromdrawing too much current becomes a possibility. Even if the power supplyis not unduly stressed, a component which uses more power than a similarcomponent will release more heat, thereby increasing the temperature ofthe component as well as the inside of the computer or electronicdevice. Elevated temperatures within the component or within the chassisof a computer can cause other components in the computer to operate moreslowly or to fail prematurely.

[0006] Reducing the amount of current used by the components in acomputer is also a concern to designers of portable computers. Thelength of time between battery recharges for various brands and types ofcomputers ranges from about two hours to 12 hours. Reducing the amountof current the computer uses, thereby extending the length of time thecomputer can-be run off the battery, is a design concern as well as amarketing concern.

[0007] For the reasons listed above, reducing the power consumption ofcomponents installed in a computer is a goal of computer componentdesigners and computer manufacturers.

SUMMARY OF THE INVENTIONS

[0008] An object of this invention is to provide a memory module designwhich uses less power than previous modules.

[0009] This object of the present invention is attained by fabricating amodule using a number of memory chips, where each memory chip can beaccessed independently, and where only the DRAM or DRAMs accessed isturned on while all other DRAMs remain in standby mode. A DRAM instandby mode uses much less current than activating the DRAM.

[0010] The invention can be applied to modules using DRAMs with multipledata outs (DQ's), but does not apply to modules using DRAMs in a x1configuration. For instance, if a module supplying 1 MB of memorycontains eight 1Mx1 DRAMs is installed in an 8-bit computer, all eightDRAMs would have to be accessed simultaneously to supply the computerwith 8 bits of data. On a 1 MB module using eight 256Kx4, only two DRAMswould have to be accessed to supply the 8-bit computer with 8 bits ofdata.

[0011] Chips containing x16 data widths have recently been developed byMicron Technology, Inc. To manufacture these 64Kx16 DRAMs, a currentgeneration 1M die is packaged with 16 DQ pins to provide a chip in a64Kx16 configuration. Each of the 1,048,576 bits are uniquely addressedthrough the 16 address bits multiplexed on eight address lines (A0-A7)during a read or a write cycle.

[0012] A common memory configuration supplying 16 bits of data is to usetwo modules with each module comprising eight 1Mx1 devices. A read cyclefrom two of these modules, as stated previously, requires about 640 mAof current. A functional equivalent of these modules would be twomodules with each module comprising eight 64Kx16 DRAMs. If theseequivalent modules not comprising the invention are used, all 16 DRAMswould be turned on during a read cycle, even though the desired datacomes from a single DRAM. A read would require 1280 mA of current. Amodule of this type comprising the invention, however, would enable onlyone DRAM during a read, thereby using about 90 mA of current.

[0013] When used in applications where an additional bit is used, as forparity, the additional bit may either be incorporated into the multipledata out (DQ) architecture as an additional DQ connection.Alternatively, partially operational DRAMs may be used, provided atleast one good sector may be addressed.

[0014] A module of this type would have signals conforming to JEDECstandards or, in custom uses, to specifications specific to the intendeduse of the module. In any case, a module containing eight 64Kx16 deviceswould require one CAS line and eight RAS lines. The CAS line selects thedesired column number in each of the eight DRAMs. The RAS lines are usedas a bank select with each RAS line being used only by a single device,thereby accessing a row address from a single DRAM.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 shows an overview of the circuitry of the inventive module;

[0016]FIG. 2 details the decode circuitry of FIG. 1;

[0017]FIG. 3 shows a simple circuit which disables the write-per-bitmode of a DRAM containing multiple DQ's;

[0018] Table 1 shows the logic associated with the signals AR9 and AC9which selects one of four groups of RAS signals;

[0019] Table 2 shows the logic associated with the signals AR8 and AC8which selects a single DRAM from a group of four DRAMs; and

[0020] Table 3 shows the logic associated with the write-per-bit lockoutcircuit of FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0021]FIG. 1 shows an overview of the circuitry of the inventive module,including the data bus (DQ1-DQ16), the address bus (AD0-AD7), and outputenable (OE). The address bus allows the computer to select individualDRAM cells to be written to or read from, while data is passed betweenthe computer and the DRAMs along the bidirectional data bus. The OEsignal controls the output buffers of the DRAM. During a READ cycle, thedata is output on the data bus when the OE signal goes low.

[0022] All DRAMs share a single write enable (WE) signal, a singleV_(CC), a common V_(SS), and a common CAS.

[0023] The signals AR8, AR9, AC8, and AC9 output by the computer to themodule are altered by the decode circuitry (described below) to functionas 16 RAS lines, which select one of 16 DRAMs on the module. Note thatFIG. 1 shows eight RAMs; RAMs 9-16 operate in a fashion similar to RAMs1-8, being addressed by RAS9-RAS16 as shown.

[0024] The Decode Circuitrv

[0025] Following JEDEC standards, a computer or electronic device hasonly one RAS and one CAS input to a memory module. With only these twoinputs, every time the electronic device accesses the memory, the sameaddress on every DRAM is read or written, and as a result every deviceturns on. In a module comprising x1 DRAMs, this is not a problembecause, as stated previously, a 16-bit computer needs to access all 16x1 DRAMs in order to receive the 16 bits of data it is capable ofhandling. In a module comprising DRAMs with multiple DQ's, however, notevery DRAM is accessed, but every DRAM is turned on. This requires thatpower be used unnecessarily.

[0026] In the inventive module, turning on all the DRAMs would defeatthe purpose of the invention, which is to save power by turning on onlythose RAMs that are accessed. The decode circuitry in FIG. 2 solves thisproblem by using the two RAS address select bits (AR8 and AR9) and thetwo CAS address select bits (AC8 and AC9) output from the computer tothe module in conjunction with the decode circuitry of FIG. 2 to turn ona single device. As shown, the two bits input on AR9 and AC9 are used toselect one of four RAS signals internal to the decode circuitry, RASA,RASB, RASC, or RASD, depending on the state of the two bits as shown inTable 1.

[0027] Each of the four groups of signals in Table 1, RASA, RASB, RASC,and RASD have four unique RAS signals as shown in FIG. 2 which areinternal to the decode circuitry and are output to the DRAMs. Referringto FIG. 2, after either RASA, RASB, RASC, or RASD is turned on, the bitssupplied on AR8 and AC8 are used to select a single location from RAS1through RAS16, each RAS line corresponding to a unique DRAM (not shown).Table 2 shows the decode logic which selects a specific DRAM. As shownin FIG. 2, RASA is divided into RAS1-RAS4, RASB is divided intoRAS5-RAS8, RASC is divided into RAS9-RAS12, and RASD is divided intoRAS13-RAS16. So, for example, if AR9 goes high and AC9 is a low, thesignal RASC goes high. Then, if both AR8 and AC8 go high, RAS12 goeshigh and accesses its associated DRAM, thereby leaving RAS1-RAS11 andRAS13-RAS16 unselected and the 15 DRAMs corresponding to those RAS linesin a power-conserving standby mode.

[0028] Overcoming Write-Per-Bit Mode

[0029] Write-per-bit mode is an industry standard on DRAMs havingmultiple DQ's. A DRAM with multiple DQ's can be written to in either anormal write mode or in write-per-bit mode. When a DRAM with more thanone DQ is in a normal write mode, the number of bits corresponding tothe number of DQ's are written at the same time. On a x16 device, forexample, the chip logic begins writing one bit of data onto each of the16 DQ's at the falling edge of CAS or WE (whichever is later) as long asRAS is low. (During a normal write, the status of WE is a “don't care”when RAS initially goes low.) The address signals, RAS, and CAS thentoggle to select the proper address to be written to, and the desireddata is input through the Data In (Din) signals.

[0030] During a write-per-bit (also called a “masked write”), anycombination (or even all) of the 16 bits can be written to withoutwriting to any of the other locations. To set up a write-per-bit signal,WE goes low. Next, the data for the “mask” is set on the DQ's, with alogic 1 corresponding to “write” and a logic 0 corresponding to a “don'twrite” (the mask data simply indicates which of the locations are to bewritten, and which are to be left unaltered). After the data for themask is set, RAS drops, and the mask information on the data lines ischanged to the desired data to be written to the selected locations.Finally, when CAS is pulled low, the write begins. The address signals,RAS, and CAS toggle to input the data into the correct addresses.

[0031] As can be seen from the above, users of memory modules whichcontain x1 DRAMS which don't use write-per-bit mode may consider WE a“don't care” as RAS goes low, and allow WE to toggle. Depending on thestate of the other signals, the unwary user may put the modulecontaining DRAMs with multiple DQ's into write-per-bit mode (which, aspreviously stated, occurs at the DRAM level if RAS goes low when WE islow). The simple circuit of FIG. 3, if incorporated into the decodecircuitry of the module or into the design of the electronic deviceusing the inventive module, will make the WE signal a don't care exceptwhen RAS is low, thereby preventing the chips on the modules fromentering write-per-bit mode. The circuit incorporates a three input NANDgate 10. RAS, WE, and a RAS signal delayed by the three NAND gates 12,14, 16 as shown in FIG. 3 are inverted, input to the NAND gate 10, andoutput as WE(out). (Note that three NAND gates is not an absolute—thenumber of NAND gates is determined only by the delay required to ensurethat WE does not go low until after RAS goes low.) The truth table forthe circuit of FIG. 3 is shown in Table 3.

[0032] A jumper, electronic switch, or a functional equivalent 18incorporated into the circuit would allow users who desire thewrite-per-bit mode to disable the circuit, thereby enablingwrite-per-bit mode to the DRAMs.

[0033] While a preferred embodiment of the invention has been disclosed,various modes of carrying out the principles described herein arecontemplated as being within the scope of the following claims. Anymemory module comprising RAMs (SRAMS, DRAMs, etc.) having multiple DQ'scould have a power savings by using the invention. For instance, in 1 MBmodule comprising eight 256Kx4 RAMs, all eight DRAMs are turned on foreach read, even though the 16 bits of data are received from only fourof the DRAMs. The description of the invention could be easily modifiedby those skilled in the art for a x4 module.

[0034] In addition, modules with data widths other than those which area multiple of four are possible with the addition of another device,such as a x1 device. For example, a x17 module is possible on a modulecontaining 64Kx16 devices with the addition of a 64Kx1 device. Note thatthis device would require another RAS line, but would use the common CASsignal, and at least two devices would be turned on simultaneously toaccess the 17 bits of data required, one x16 DRAM for the 16 data bits,and the x1 device for the parity bit.

[0035] Finally, the described invention doesn't necessarily pertain onlyto memory supplied in module form. The invention would work equally wellwith memory placed directly on the motherboard (embedded memory) or withany other memory addressed by the computer.

[0036] It is therefore understood that the scope of the invention is notto be limited except as otherwise set forth in the claims.

1. A logic array for storing bits of information comprising: a) aplurality of storage devices wherein each storage device comprisesmultiple data out signals and a plurality of subarrays, the number ofsubarrays on each storage device corresponding to the number of data outsignals on said storage device, and each subarray comprising a pluralityof storage locations wherein each storage location in one of saidsubarrays has a unique coordinate, said coordinates repeated acrosssubarrays and across storage devices, wherein accessing data from saidstorage locations results in a significant increase in consumption ofcurrent by that storage device; b) means for accessing a selected numberof said storage devices in said logic array to receive multiple bits ofdata; and c) means for selecting said number of said storage devices;whereby said accessing substantially changes an amount of current usedby said accessed storage device without substantially changing an amountof current used by any unaccessed storage device in said logic array. 2.The logic array of claim 1 wherein said means for accessing one of saidstorage devices to receive multiple bits of data comprises: a) means foraddressing a storage location by specifying an x coordinate and a ycoordinate, the same x-y coordinate point on every subarray of everystorage device being addressed simultaneously thereby; and b) multipleprimary signals wherein each said storage device has an associatedunique primary signal such that by enabling one of said primary signalsmultiple data bits, one from each subarray of a single storage device,can be selected.
 3. The logic array of claim 1 wherein said accessingchanges the current used by any unaccessed storage device in said logicarray by less than 5%.
 4. The logic array of claim 2 wherein means foraddressing a storage location comprises address signals whereby addressbits on said address signals include said x and y coordinates.
 5. Amemory array for storing data bits comprising: a) a plurality of randomaccess memories (RAMs) wherein each RAM comprises multiple data outsignals and a plurality of subarrays, the number of subarrays on eachRAM corresponding to the number of data out signals on said RAM, andeach subarray comprising a plurality of memory cells wherein each memorycell in one of said subarrays has a unique coordinate, said coordinatesrepeated across subarrays and across RAMs, wherein accessing data bitsfrom said memory cells results in a significant increase in consumptionof current by that RAM; b) means for accessing a selected number of saidRAMs in said memory array to receive multiple data bits; and c) meansfor selecting said number of said RAMs; whereby said accessingsubstantially changes an amount of current used by said accessed RAMwithout substantially changing an amount of current used by anyunaccessed RAM in said memory array.
 6. The memory array of claim 5wherein said means for accessing one of said RAMs to receive multipledata bits comprises: a) means for addressing a memory cell by specifyingan x coordinate and a y coordinate, the same x-y coordinate point onevery subarray of every RAM being addressed simultaneously thereby; andb) multiple primary signals wherein each said RAM has an associatedunique primary signal such that by enabling one of said primary signalsmultiple data bits, one from each subarray of a single RAM, can beselected.
 7. The memory array of claim 5 wherein said accessing changesthe current used by any unaccessed RAM in said memory array by less than5%.
 8. The memory array of claim 6 wherein means for addressing a memorycell comprises address signals whereby address bits on said addresssignals include said x and y coordinates.
 9. A logic memory array forstoring bits of information, comprising: a) a plurality of storagedevices wherein each storage device comprises multiple data out signalsand a plurality of subarrays, the number of subarrays on each storagedevice corresponding to the number of data out signals on said storagedevice, and each subarray comprising a plurality of storage locationswherein each storage location in one of said subarrays has a unique x-ycoordinate, said coordinates repeated across subarrays and acrossstorage devices, wherein accessing data from said storage locationsresults in a significant increase in consumption of current by thatstorage device; and b) a second device connected to said storage devicessuch that the bits of information are transferrable between said storagedevices and said second device in a plurality of parallel processes,said second device having means for individually accessing each of saidstorage devices to obtain a number of the bits of information from saidstorage device which results in a substantial increase in currentconsumption by the accessed storage unit, without substantially changingthe current to any unaccessed storage units; wherein said means foraccessing each of said storage devices includes plural primary signals,with one primary signal to each of said storage devices, and a commonsecondary signal to each of said storage devices, said primary signalselecting a single x coordinate from its associated storage device andsaid secondary signal selecting a y coordinate from said storagedevices.